CMOS mixed-mode integrated circuits are a topic of increasing interest and importance. The present trend is towards mixed-mode monolithic systems containing higher frequency and higher accuracy analog circuitry combined with increasingly complex digital circuitry. Examples of such circuitry include 16-20 bit self-correcting successive-approximation converters and sigma-delta analog-to-digital (A/D) converters. The achievable accuracy of many such systems is now limited by the adverse effects of digital switching noise associated with conventional CMOS static logic circuitry. In the future, this problem will become proportionately worse at higher frequencies due to the unavoidable reduction in the power supply noise rejection capabilities of the analog circuitry at higher frequencies.
CMOS static logic is widely used because of its high packing densities, noise margins, and operating frequencies. Although a conventional CMOS logic gate ideally dissipates zero static power, a large overlap current pulse (.about.1 mA/gate) flows from V.sub.dd to GND during its state transition. Large current pulses flowing through the inductances and resistances associated with the substrate, power supply lines, bonding wires, package pins, etc., typically cause 1 volt or more of switching noise on the V.sub.dd and GND lines. The accuracy of mixed-mode ASIC's is often limited by the coupling of the switching noise into the analog circuitry that shares the same substrate (FIG. 9).
One way to increase the accuracy of mixed-mode ASIC's is to increase the power supply noise rejection capabilities of the analog circuitry. With fully-differential analog architectures, power supply noise appears as a common-mode signal that is rejected by the common-mode-rejection-ratio (CMRR). However, CMRR usually decreases in direct proportion to increases in frequency.
A reduction in the transmission of digital switching noise between the digital and analog subsections may be obtained by using guardbanding and/or power supply separation techniques. Separate analog and digital power supply lines are used to minimize the common impedance.
Further success in reducing the transmission of switching noise between the analog and digital subsections is determined by the nature of the power supply connections to the substrate. When laying out digital cells using a p-well CMOS technology, it is common practice to incorporate within each cell several n.sup.+ ohmic contacts from the digital V.sub.dd supply line to the substrate to deter latch-up. Hence, switching noise associated with digital V.sub.dd is unavoidably coupled directly into the analog circuitry via the common substrate.
Significant increases in the accuracy of mixed-mode systems may also be achieved by reducing the amount of switching noise generated by the digital logic. The switching noise associated with conventional logic originated with the overlap current pulses generated during transitions. More precisely, the switching noise arises because the power supply currents are not constant. One way to implement logic circuits with constant supply currents is to use MOS differential pairs to switch constant current sources. Such a technique is disclosed in copending application Ser. No. 07/693,532 entitled MOS Folded Source-Coupled Logic. Although this approach achieves low power-supply noise, it requires several additional transistors per gate, and the MOSFETs are required to have large W/L ratios at high frequencies.
In accordance with the present invention, switching current transients in mixed mode circuitry are greatly minimized by use of source-coupled differential CMOS logic circuits wherein a constant DC bias current is steered to change logic states. Internal voltage swings are typically less than one volt. Consequently, measured power supply (V.sub.dd) current spikes are typically only 15 .mu.A for current steering inverter implemented in a 2 .mu.m p-well CMOS technology--a reduction of two orders of magnitude compared to the 1.5 mA current spikes typical of a conventional static CMOS inverter. The reduction in digital switching noise allows the development of higher performance on-chip analog circuitry in CMOS mixed-mode applications.
The foregoing and additional features and advantages of the invention will be more readily apparent from the following detailed description, which proceeds with reference to the accompanying drawings.